1. Field of the Invention
The present invention relates to a memory system; in particular, to a memory system having a hybrid density memory, and methods for wear-leveling management and file distribution management thereof.
2. Description of Related Art
As technologies advance, demand for data storage capacity increases incessantly. Among the non-volatile memories (or referred as electricity-independent memory) used for data storage, flash memory presents advantages of high storage density, low power consumption, effective access efficiency and reasonable price, thus becoming the most commonly adopted storage media nowadays. Flash memory with tight and rigid structure is suitable for being installed within electric devices, including digital camera, digital cam, digital music player, hand-held personal computer and GPS etc, or may be fabricated as storage device like memory card and thumb drive.
Although flash memory provides many advantages, there exist two restrictions in hardware. First, flash memory is read and programmed to operate in the unit of pages and erased in the unit of blocks. A block of flash memory, before re-writing data therein, must be erased in advance to perform re-write, and direct overwrite is not possible. Second, since the erase action must be performed under higher voltage, the erase count that flash memory can endure is limited. The limit on memory erase count is generally referred as the memory endurance cycle. As the accumulated erase count of a block approaches to the erase count limit, it is probable to result in write failure, reducing the data access reliability. Therefore, wear-leveling technology has been developed for controlling the data storage in flash memory, which allows the erase counts of all memory blocks in memory to be consistent as much as possible, enabling effective usage of all blocks in memory.
The memory records the stored bit values by voltage values conserved in memory cells. In traditional memory storage technology, a bit data as one (1) or zero (0) is record by means of high level or zero level of the voltage value conserved in one memory cell. As semi-conductor manufacture technology develops, the level values conserved within memory cell can be further divided, so as to store more bit data. For example, if a memory cell can retain four different level values, it is possible to store two-bit data; in case that a memory cell can conserve sixteen different level values, then it can store four-bit data. The industry refers the traditional memory manufacture technology for storing one single bit data as the Single-Level-Cell (SLC) process, and memory manufacture technology for storing multi-bit data as the Multi-Level-Cell (MLC) process; memory fabricated by adopting the SLC process as low density memory, and memory fabricated through the MLC process as high density memory.
Compared with low density memory, the data storage capacity provided within a unit area of high density memory increases multifold. Since high density memory provides desirable advantages in terms of price and storage capacity, the current memory card and thumb drive hence commonly adopt high density memory as data storage. Although MLC process creates high storage capacity of high density memory, the storage features thereof nonetheless comparatively deteriorate, in which the main defects comprise significant reductions in erase endurance and access rate. The erase endurance of memory closely relates to the employed manufacture technology. Currently, the erase endurance of low density memory available in market is about 100,000 times, whereas the erase endurance for high density memory generally 10,000 times, showing a difference by a factor of 10. Based on this reason, while the industry employs high density memory to significantly increase the storage capacity of storage devices, the serious defect of dramatic shrinkage in life span also emerges.
In view that the advantages of high density memory lie in high storage capacity and low cost, and advantages of low density memory exist in high erase endurance and fast access rate, each type of memory respectively demonstrates features thereof, the industry therefore has developed in recent years a hybrid density memory. As can be appreciated from its name, said hybrid density memory is configured with both high density memory and low density memory. As for exploiting advantages provided by both types of memory to optimize the performance of hybrid density memory has now become one major research subject aggressively devoted by relevant industry.
U.S. Pat. No. 6,807,106 (referred hereunder as the '106) proposed a data storage technology for hybrid density memory. Referring now to FIGS. 1A and 1B, these Figures illustrate a diagram of storage management for hybrid density memory proposed by the '106. FIGS. 1A and 1B depict a corresponding conversion relationship between logical positions and physical positions of file data storage; that is, the relationship between the address space of a data and a physically stored memory position thereof. As shown in FIG. 1A, the logical block 10 consists of a header area 100 and a data area 105. The data area 105 contains the actual contents of the data, and the header area 100 is used for relevant control information, e.g., information for describing the correctness or other attributes of the data in the data area 105. FIG. 1B shows distribution of the physical block 12 to which the logical block 10 in FIG. 1A corresponds. As illustrated in FIG. 1B, the header area 100 and data area 105 of the logical block 10 are respectively distributed to a low density memory block 120 and a high density memory block 125. The '106 is directed to frequent access of the data stored in the header area 100, hence the data of the header area 100 is stored in the low density memory block 120 for faster access rate, and the data area 105 occupying more space is stored in the high density memory block 125, so as to enhance the data access performance of hybrid density memory. Although the technical solution proposed by the '106 is able to enhance the access performance of file data stored inside hybrid density memory, the technology did not meet the requirement on wear-leveling of block, thus the life span of the storage device is restricted by the high density memory with less erase endurance. In the '106, once the file data is updated, the header area 100 and the data in the data area 105 will be updated together and, collaterally, one erase action must be also performed onto both the low density memory block 120 as well as the high density memory block 125. Referring to FIG. 2, a diagram of erase count for the '106 is shown. In FIG. 2, block positions L1 and H1 respectively illustrate the erase counts of the low density memory block 120 and the high density memory block 125. The erase endurance counts for the low density memory block and the high density memory block are individually referred as EC2 and EC1. Though hybrid density memory storage is composed of multiple high density memory blocks and multiple low density memory blocks, herein a single high density memory block and a single low density memory block are used to explain the reason why the '106 did not meet the requirement on wear-leveling.
As shown in FIG. 2, when the storage device is in use, the erase counts of the block positions L1 and H1 increase at the same time; as the accumulated erase counts for both of them reach the erase endurance count EC1 of the high density memory block, the high density memory block may be disabled to perform the function of data storage. Collaterally, since the erase count in the high density memory block has reached its limit, the storage device may fail. However, upon the failure of the storage device, the erase count in the low density memory block has not yet reached its endurance count EC2. Besides, taking the endurance counts EC2 and EC1 as respectively 100,000 and 10,000 times for example, the erase count in the low density memory block has merely reached 10 percents of the endurance count thereof, which wastes the reset 90 percents of available storage resources. Obviously, the technology proposed in the '106 did not meet the requirement on wear-leveling, resulting in wastes of memory resources.
U.S. Pat. Nos. 6,081,447, 6,230,233, 6,594,183, 6,831,865, 6,850,443, 6,985,992 proposed several wear-leveling technologies, but none provided practical solutions for wear-leveling directed to hybrid density memory. Regarding the aforementioned issues, the inventors thus propose the present invention, expecting to fully exploit and optimize the storage resource usage of hybrid density memory.